By Jason Cong, Sachin Sapatnekar, Yuan Xie
This publication offers the reader with a whole knowing of why 3 dimensional IC layout is a promising technique to proceed functionality scaling, the potential how you can do 3D integration (fabrication), the EDA demanding situations and strategies to facilitate designers to do 3D IC layout, the architectural advantages of utilizing 3D expertise, and the layout matters on the structure point. The paintings covers the historical past on 3D integration, fabrication thoughts for 3D ICs, EDA flows and algorithms for 3D layout, structure point layout innovations for 3D microarchitecture. The booklet comprises an advent at the historical past of 3D IC, a motivation that explains why the 3D IC is necessary and the way it is going to pattern, 3D strategy (fabrication) thoughts, 3D EDA algorithms and instruments (physical point and architectural point tools), 3D microarchitecture, together with 3D FPGA, 3D unmarried core/multi middle processors, 3D Network-onchip designs.
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Although those methods decrease the complexity of the matter, they could lose the optimality by way of proscribing the layer project in the course of optimization. the following we introduce a flat layout framework  within which the layer assignments and the floorplans of every layer are decided at the same time. consequently, the block should be moved from one layer to a different throughout the looking technique. With the representations brought within the prior part, we will practice the SA optimization scheme to 3D floorplanning with 2nd blocks. To layout an effective SA scheme, there are numerous matters that are severe. 1. illustration of the answer: because the packing on every one layer may be represented via a second illustration, the multi-layer packing could be represented by way of an array of 2nd representations and blocks are moved within each one layer or swapped among layers for answer perturbations. yet to beat boundaries attributable to the shortcoming of relative place info of blocks on diverse layers, we may perhaps encode the Z-direction neighboring info utilizing an extra bucket constitution. In each one bucket i, indexes of the blocks that intersect with the bucket are saved; the index set is often called IB(i), regardless of which layer the block is on. meanwhile, each one block j shops indexes to all buckets that overlap with the block; the index set is known as IBT(j). as a result, the mixed bucket and 2nd array (CBA) is proposed; this can be composed of 2 elements – a second floorplan illustration used to symbolize each one layer, and a bucket constitution to shop the vertical courting among blocks. during this bankruptcy we decide TCG to symbolize the 2nd packing on each one layer. 2. Cooling agenda: the full cooling agenda contains the manage of the preliminary temperature, cooling functionality, and finish temperature. It is dependent upon the scale of the matter and the valuables of the matter. three. resolution perturbation: We take the CBA illustration as an instance. There are seven varieties of operations on CBA, as proven within the following: – – – – Rotation, which rotates a block switch, which swaps blocks in a single layer opposite, which exchanges the relative place of 2 blocks in a single layer circulation, which strikes a block from one facet (such as best) of a block to a different part (such as left) – Inter-layer switch, which swaps blocks at varied layers – z-neighbor switch, which swaps blocks at diverse layers yet on the subject of one another – z-neighbor movement, which strikes a block to a place at one other layer as regards to the present place 86 J. Cong and Y. Ma four. fee functionality: each time a block configuration is generated, a weighted price of the optimization goals and the restrictions should be evaluated. the associated fee functionality should be written as rate = αWL + βArea + γ Nvia + θ T the place WL is the wirelength estimation utilizing a part perimeter version, region is the made of the maximal peak and width over all layers, Nvia is the variety of inter-layer vias, and T is the maximal temperature. right here in 3D designs, the on-chip temperature is so excessive that it is crucial to account for the closed temperature/leakage strength suggestions loop to correctly estimate or optimize both one.