By Siva G. Narendra
Covers intimately promising recommendations on the equipment, circuit, and structure degrees of abstraction after first explaining the sensitivity of a number of the MOS leakage resources to those stipulations from the 1st ideas.
Also handled are the ensuing results so the reader is familiar with the effectiveness of leakage energy aid recommendations below those assorted stipulations.
Case reviews offer real-world examples that benefit from leakage strength aid options because the ebook highlights diversified gadget layout offerings that exist to mitigate raises within the leakage elements as expertise scales.
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Extra resources for Leakage in Nanometer CMOS Technologies (Integrated Circuits and Systems)
Traditional 1. 28 mA Proposed jPower down j I self refresh J zero. 21 mA T= seventy five °C five = 109 mV/decade (p-MOST) 89 mV/decade (n-MOST) P^r= zero. 03 V (p-MOST) -0. 02 V (n-MOST) l6z7=2. 0V, l/p//=3. 8V, VBB=-iy Fig. 7-17 Leakage within the standby mode of 256-Mb SDRAM . The peripheral circuits part is from peripheral MOSTs with no substrate bias. pace penalty, as formerly mentioned. A ensuing S as small as 254 mV lowered the standby sub-threshold present of the word-driver and decoder blocks to one. 5x10"^ for n = 256 and W(Qs)/W(Qp) = five, permitting to lessen the sub-threshold present of the chip to three% (from 219 to six |LIA). the full information retention present was once hence decreased to fifty three |LiA. The small S enabled a quick restoration time to the lively mode of one ns. determine 7-16 indicates one other 256-lVIb DRAIVI  with a hierarchical word-line structure . The SSI and multi-static excessive Vj using good biases were mixed. right here, /MWL and SWL are the most observe line and sub-word line, and CSL is the column decide upon line for the multi-divided data-line structure . The turned around MOSFETs within the determine are within the subthreshold sector through the standby mode. the following, SSIi used to be basically utilized to the p-MOSFETs (open circles) within the inverter chain with an output of RX in 188 Leakage in Nanometer CMOS applied sciences SSI2- OHBVDH SSIi' O-HB" Voo-JB SSI2 0SSIi O n i i / ? / VDH VDD^ P l/cwH&i^/ VpH-^Xai (Selectecf) ^ * I NANbi FWI niml VDD^ SSIi 1^^'HC SSI2 OHI (a) (b) Fig. 7-18 observe driving force block (a) and decoder block (b) with the hierarchical SSI scheme [13, 14]. the array keep an eye on circuit, which corresponds to determine 7-7(a). This used to be simply because p-MOSFETs have a bigger overall channel width and a bigger 5-factor (see determine 7-17) because of their buried-channel MOSFET constitution. seeing that those inverters function in sequence within the time area, this connection doesn't reason a velocity penalty, as formerly defined. SSIi used to be additionally utilized to the mainword driving force block. in addition, the n-MOSFETs (shaded circles) and pMOSFETs (shaded circles) within the column-decoder block had the next VV as a result respective good bias VBB and VDH- SSI2 extra decreased the leakage within the column decoder block. through combining either SSI and multi-static high-VV schemes, the full sub-threshold present within the power-down/self-refresh mode was once lowered to one-sixth, as determine 7-17 indicates. the present can additional be decreased through using a multi-static VT scheme to the peripheral circuits. Active-current relief of 16-Gb DRAM: Hierarchical SSI schemes (i. e.. desk 7-2(d)) and an influence swap have been potent in decreasing the lively present of a hypothetical 1-V 16-Gb DRAM [13, 14]. Figures 7-18(a) indicates software to the word-driver block [13, 14], that's divided into m subblocks with n/m observe drivers every one. An SSIi is hooked up to the typical resource line of p-MOSFET observe drivers to pick the sub-block. within the lively mode, whereas turning at the chosen SSII and SSI2, the leakage in every one nonselected sub-block is constrained to the SSIi small consistent present because the SSIi channel width is way narrower than the whole channel width of motive force MOSFETs within the corresponding sub-block, as formerly mentioned.